Linux "as" Command Line Options and Examples
the portable GNU assembler.
GNU as is really a family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.
Usage:
as [-a[cdghlns][=file]] [--alternate] [-D]
[--compress-debug-sections] [--nocompress-debug-sections]
[--debug-prefix-map old=new]
[--defsym sym=val] [-f] [-g] [--gstabs]
[--gstabs+] [--gdwarf-2] [--gdwarf-sections]
[--help] [-I dir] [-J]
[-K] [-L] [--listing-lhs-width=NUM]
[--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]
[--listing-cont-lines=NUM] [--keep-locals]
[--no-pad-sections]
[-o objfile] [-R]
[--hash-size=NUM] [--reduce-memory-overheads]
[--statistics]
[-v] [-version] [--version]
[-W] [--warn] [--fatal-warnings] [-w] [-x]
[-Z] [@FILE]
[--sectname-subst] [--size-check=[error|warning]]
[--elf-stt-common=[no|yes]]
[--target-help] [target-options]
[--|files ...]
Command Line Options:
-a[cdghlmns]
Turn on listings, in any of a variety of ways:
as -a[cdghlmns] ...
-ac
omit false conditionals
as -ac ...
-ad
omit debugging directives
as -ad ...
-ag
include general information, like as version and options passed
as -ag ...
-ah
include high-level source
as -ah ...
-al
include assembly
as -al ...
-am
include macro expansions
as -am ...
-an
omit forms processing
as -an ...
-as
=fileset the name of the listing fileYou may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used,must be the last one. By itself, -a defaults to -ahls.
as -as ...
--alternate
Begin in alternate macro mode.
as --alternate ...
--compress-debug-sections
Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatiblewith older linkers and object file utilities. Note if compression would make a given section larger then it is not compressed.
as --compress-debug-sections ...
--nocompress-debug-sections.
--compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to
as --nocompress-debug-sections. ...
--nocompress-debug-sections
Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure timeoption can be used to override this.
as --nocompress-debug-sections ...
-D
Ignored. This option is accepted for script compatibility with calls to other assemblers.
as -D ...
--debug-prefix-map
When assembling files in directory old, record debugging information describing them as in new instead.
as --debug-prefix-map ...
--defsym
Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0xindicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside asource file via the use of a ".set" pseudo-op.
as --defsym ...
-f
"fast"---skip whitespace and comment preprocessing (assume source is compiler output).
as -f ...
--gen-debug
Generate debugging information for each assembler source line using whichever debug format is preferred by the target. Thiscurrently means either STABS, ECOFF or DWARF2.
as --gen-debug ...
--gstabs
Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handleit.
as --gstabs ...
--gstabs+
Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and thatcould make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNUextension is the location of the current working directory at assembling time.
as --gstabs+ ...
--gdwarf-2
Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger canhandle it. Note---this option is only supported by some targets, not all of them.
as --gdwarf-2 ...
--gdwarf-sections
Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the correspondingcode section. For example a code section called .text.func will have its dwarf line number information placed into a sectioncalled .debug_line.text.func. If the code section is just called .text then debug line section will still be called just.debug_line without any suffix.
as --gdwarf-sections ...
--size-check
Issue an error or warning for invalid ELF .size directive.
as --size-check ...
--elf-stt-common
These options control whether the ELF assembler should generate common symbols with the "STT_COMMON" type. The default can becontrolled by a configure option --enable-elf-stt-common.
as --elf-stt-common ...
--help
Print a summary of the command line options and exit.
as --help ...
--target-help
Print a summary of all target specific options and exit.
as --target-help ...
-I
Add directory dir to the search list for ".include" directives.
as -I ...
-J
Don't warn about signed overflow.
as -J ...
-K
Issue warnings when difference tables altered for long displacements.
as -K ...
--keep-locals
Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELFsystems or L for traditional a.out systems.
as --keep-locals ...
--listing-lhs-width
Set the maximum width, in words, of the output data column for an assembler listing to number.
as --listing-lhs-width ...
--listing-lhs-width2
Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
as --listing-lhs-width2 ...
--listing-rhs-width
Set the maximum width of an input source line, as displayed in a listing, to number bytes.
as --listing-rhs-width ...
--listing-cont-lines
Set the maximum number of lines printed in a listing for a single line of input to number + 1.
as --listing-cont-lines ...
--no-pad-sections
Stop the assembler for padding the ends of output sections to the alignment of that section. The default is to pad the sections,but this can waste space which might be needed on targets which have tight memory constraints.
as --no-pad-sections ...
-o
Name the object-file output from as objfile.
as -o ...
-R
Fold the data section into the text section.
as -R ...
--hash-size
Set the default size of GAS's hash tables to a prime number close to number. Increasing this value can reduce the length of timeit takes the assembler to perform its tasks, at the expense of increasing the assembler's memory requirements. Similarlyreducing this value can reduce the memory requirements at the expense of speed.
as --hash-size ...
--reduce-memory-overheads
This option reduces GAS's memory requirements, at the expense of making the assembly processes slower. Currently this switch isa synonym for --hash-size=4051, but in the future it may have other effects as well.
as --reduce-memory-overheads ...
--sectname-subst
Honor substitution sequences in section names.
as --sectname-subst ...
--statistics
Print the maximum space (in bytes) and total time (in seconds) used by assembly.
as --statistics ...
--strip-local-absolute
Remove local absolute symbols from the outgoing symbol table.
as --strip-local-absolute ...
-version
Print the as version.
as -version ...
--version
Print the as version and exit.
as --version ...
--no-warn
Suppress warning messages.
as --no-warn ...
--fatal-warnings
Treat warnings as errors.
as --fatal-warnings ...
--warn
Don't suppress warning messages or treat them as errors.
as --warn ...
-Z
Generate an object file even after errors.
as -Z ...
--
Standard input, or source files to assemble.The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64).
as -- ...
-EB
This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
as -EB ...
-EL
This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
as -EL ...
-mabi
Specify which ABI the source code uses. The recognized arguments are: "ilp32" and "lp64", which decides the generated objectfile in ELF32 and ELF64 format respectively. The default is "lp64".
as -mabi ...
-mcpu
This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble aninstruction which will not execute on the target processor. The following processor names are recognized: "cortex-a35","cortex-a53", "cortex-a55", "cortex-a57", "cortex-a72", "cortex-a73", "cortex-a75", "exynos-m1", "falkor", "qdf24xx", "saphira","thunderx", "vulcan", "xgene1" and "xgene2". The special name "all" may be used to allow the assembler to accept instructionsvalid for any supported processor, including all optional extensions.In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics thatextend the processor.If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled.Consequently, you will not normally have to specify any additional extensions.
as -mcpu ...
-march
This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble aninstruction which will not execute on the target architecture. The following architecture names are recognized: "armv8-a","armv8.1-a", "armv8.2-a", "armv8.3-a" and "armv8.4-a".If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assemblerwill default to -mcpu=all.The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu,extensions are not always enabled by default,
as -march ...
-mverbose-error
This option enables verbose error messages for AArch64 gas. This option is enabled by default.
as -mverbose-error ...
-mno-verbose-error
This option disables verbose error messages in AArch64 gas.The following options are available when as is configured for an Alpha processor.
as -mno-verbose-error ...
-no-mdebug
Enables or disables the generation of ".mdebug" encapsulation for stabs directives and procedure descriptors. The default is toautomatically enable ".mdebug" when the first stabs directive is seen.
as -no-mdebug ...
-relax
This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations atassembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbolarithmetic can be represented. However, the option can still be useful in specific applications.
as -relax ...
-noreplace
Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only availablefor VMS targets and "-replace" is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.
as -noreplace ...
-Gsize
A local common symbol larger than size is placed in ".bss", while smaller symbols are placed in ".sbss".
as -Gsize ...
-32addr
These options are ignored for backward compatibility.The following options are available when as is configured for an ARC processor.
as -32addr ...
-mcode-density
Enable Code Density extenssion instructions.The following options are available when as is configured for the ARM processor family.
as -mcode-density ...
-mfpu
Select which Floating Point architecture is the target.
as -mfpu ...
-mfloat-abi
Select which floating point ABI is in use.
as -mfloat-abi ...
-mthumb
Enable Thumb only instruction decoding.
as -mthumb ...
-mapcs-32
Select which procedure calling convention is in use.
as -mapcs-32 ...
-mthumb-interwork
Specify that the code has been generated with interworking between Thumb and ARM code in mind.
as -mthumb-interwork ...
-mccs
Turns on CodeComposer Studio assembly syntax compatibility mode.
as -mccs ...
-k
The following options are available when as is configured for the Blackfin processor family.
as -k ...
-mfdpic
Assemble for the FDPIC ABI.
as -mfdpic ...
-mnopic
Disable -mfdpic.See the info pages for documentation of the CRIS-specific options.The following options are available when as is configured for a D10V processor.
as -mnopic ...
-O
The following options are available when as is configured for a D30V processor.
as -O ...
-n
Warn when nops are generated.
as -n ...
-N
The following options are available when as is configured for an Epiphany processor.
as -N ...
-mepiphany
Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior.
as -mepiphany ...
-mepiphany16
Restricts the permitted instructions to just the 16 bit set.The following options are available when as is configured for an H8/300 processor. @chapter H8/300 Dependent FeaturesOptionsThe Renesas H8/300 version of "as" has one machine-dependent option:
as -mepiphany16 ...
-h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
as -h-tick-hex ...
-mach
Sets the H8300 machine variant. The following machine names are recognised: "h8300h", "h8300hn", "h8300s", "h8300sn", "h8300sx"and "h8300sxn".The following options are available when as is configured for an i386 processor.
as -mach ...
--32
Select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64architecture with 32-bit or 64-bit word-size respectively.These options are only available with the ELF object file format, and require that the necessary BFD support has been included(on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).
as --32 ...
--divide
On SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions.The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, oraffect using # for starting a comment.
as --divide ...
-mtune
This option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of theprocessor specified by the -march option will be generated.Valid CPU values are identical to the processor list of -march=CPU.
as -mtune ...
-msse2avx
This option specifies that the assembler should encode SSE instructions with VEX prefix.
as -msse2avx ...
-msse-check
These options control if the assembler should check SSE instructions. -msse-check=none will make the assembler not to check SSEinstructions, which is the default. -msse-check=warning will make the assembler issue a warning for any SSE instruction.
as -msse-check ...
-mavxscalar
These options control how the assembler should encode scalar AVX instructions. -mavxscalar=128 will encode scalar AVXinstructions with 128bit vector length, which is the default. -mavxscalar=256 will encode scalar AVX instructions with 256bitvector length.
as -mavxscalar ...
-mevexlig
These options control how the assembler should encode length-ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG EVEXinstructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructionswith 256bit and 512bit vector length, respectively.
as -mevexlig ...
-mevexwig
These options control how the assembler should encode w-ignored (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEXinstructions with evex.w = 0, which is the default. -mevexwig=1 will encode WIG EVEX instructions with evex.w = 1.
as -mevexwig ...
-mmnemonic
This option specifies instruction mnemonic for matching instructions. The ".att_mnemonic" and ".intel_mnemonic" directives willtake precedent.
as -mmnemonic ...
-msyntax
This option specifies instruction syntax when processing instructions. The ".att_syntax" and ".intel_syntax" directives willtake precedent.
as -msyntax ...
-mnaked-reg
This option specifies that registers don't require a % prefix. The ".att_syntax" and ".intel_syntax" directives will takeprecedent.
as -mnaked-reg ...
-madd-bnd-prefix
This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in thesource code.
as -madd-bnd-prefix ...
-mno-shared
On ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets withdefault visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option onlyaffects the handling of branch instructions.
as -mno-shared ...
-mbig-obj
On x86-64 PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections.
as -mbig-obj ...
-momit-lock-prefix
These options control how the assembler should encode lock prefix. This option is intended as a workaround for processors, thatfail on lock prefix. This option can only be safely used with single-core, single-thread computers -momit-lock-prefix=yes willomit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default.
as -momit-lock-prefix ...
-mfence-as-lock-add
These options control how the assembler should encode lfence, mfence and sfence. -mfence-as-lock-add=yes will encode lfence,mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=nowill encode lfence, mfence and sfence as usual, which is the default.
as -mfence-as-lock-add ...
-mrelax-relocations
These options control whether the assembler should generate relax relocations, R_386_GOT32X, in 32-bit mode, orR_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX, in 64-bit mode. -mrelax-relocations=yes will generate relax relocations.
as -mrelax-relocations ...
-mevexrcig
These options control how the assembler should encode SAE-only EVEX instructions. -mevexrcig=rne will encode RC bits of EVEXinstruction with 00, which is the default. -mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX instructionswith 01, 10 and 11 RC bits, respectively.
as -mevexrcig ...
-mintel64
This option specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept both.The following options are available when as is configured for the Intel 80960 processor.
as -mintel64 ...
-ACA
Specify which variant of the 960 architecture is the target.
as -ACA ...
-b
Add code to collect statistics about branches taken.
as -b ...
-no-relax
Do not alter compare-and-branch instructions for long displacements; error if necessary.The following options are available when as is configured for the Ubicom IP2K series.
as -no-relax ...
-mip2022ext
Specifies that the extended IP2022 instructions are allowed.
as -mip2022ext ...
-mip2022
Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.The following options are available when as is configured for the Renesas M32C and M16C processors.
as -mip2022 ...
-m32c
Assemble M32C instructions.
as -m32c ...
-m16c
Assemble M16C instructions (the default).
as -m16c ...
--m32rx
Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to theM32RX.
as --m32rx ...
--warn-explicit-parallel-conflicts
Produce warning messages when questionable parallel constructs are encountered.
as --warn-explicit-parallel-conflicts ...
--no-warn-explicit-parallel-conflicts
Do not produce warning messages when questionable parallel constructs are encountered.The following options are available when as is configured for the Motorola 68000 series.
as --no-warn-explicit-parallel-conflicts ...
-l
Shorten references to undefined symbols, to one word instead of two.
as -l ...
-m68000
| -m68008 | -m68010 | -m68020 | -m68030
as -m68000 ...
-m68040
| -m68060 | -m68302 | -m68331 | -m68332
as -m68040 ...
-m68333
Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed atconfiguration time.
as -m68333 ...
-m68881
The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020,68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, sinceit's possible to do emulation of the coprocessor instructions with the main processor.
as -m68881 ...
-m68851
The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 andup.The following options are available when as is configured for an Altera Nios II processor.
as -m68851 ...
-relax-section
Replace identified out-of-range branches with PC-relative "jmp" sequences when possible. The generated code sequences aresuitable for use in position-independent code, but there is a practical limit on the extended branch range because of the lengthof the sequences. This option is the default.
as -relax-section ...
-relax-all
Replace branch instructions not determinable to be in range and all call instructions with "jmp" and "callr" sequences(respectively). This option generates absolute relocations against the target symbols and is not appropriate for position-independent code.
as -relax-all ...
-mlink-relax
Assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LDwould shorten the LDI32 instruction to a single LDI. In such case "as" will output DIFF relocations for diff expressions.
as -mlink-relax ...
-mno-link-relax
Assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted.
as -mno-link-relax ...
-mno-warn-regname-label
Do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. Ccompilers may want to turn this off.The following options are available when as is configured for a MIPS processor.
as -mno-warn-regname-label ...
-G
This option sets the largest size of an object that can be referenced implicitly with the "gp" register. It is only accepted fortargets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
as -G ...
-mips64r6
Generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an aliasfor -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2,
as -mips64r6 ...
-mips32r3
MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64Release 5, and MIPS64 Release 6 ISA processors, respectively.
as -mips32r3 ...
-mno-fix7000
Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following twoinstructions.
as -mno-fix7000 ...
-mno-fix-rm7000
Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.
as -mno-fix-rm7000 ...
-mno-pdr
Control generation of ".pdr" sections.
as -mno-pdr ...
-mfp32
The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treatedas 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
as -mfp32 ...
-mfp64
The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treatedas 64 bits wide at all times. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers.
as -mfp64 ...
-mfpxx
The register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABIvariant which will operate correctly with floating-point registers which are 32 or 64 bits wide.
as -mfpxx ...
-mno-odd-spreg
Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies
as -mno-odd-spreg ...
-no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting ".module mips16" at the start of the assembly file.
as -no-mips16 ...
-mno-mips16e2
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting ".module mips16e2" at the start of theassembly file. -mno-mips16e2 turns off this option.
as -mno-mips16e2 ...
-mno-micromips
Generate code for the microMIPS processor. This is equivalent to putting ".module micromips" at the start of the assembly file.
as -mno-micromips ...
-mno-smartmips
Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting ".module smartmips" at the start ofthe assembly file. -mno-smartmips turns off this option.
as -mno-smartmips ...
-no-mips3d
Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions.
as -no-mips3d ...
-no-mdmx
Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turnsoff this option.
as -no-mdmx ...
-mno-dsp
Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1instructions. -mno-dsp turns off this option.
as -mno-dsp ...
-mno-dspr2
Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler toaccept DSP Release 2 instructions. -mno-dspr2 turns off this option.
as -mno-dspr2 ...
-mno-dspr3
Generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells theassembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option.
as -mno-dspr3 ...
-mno-msa
Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns offthis option.
as -mno-msa ...
-mno-xpa
Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions.
as -mno-xpa ...
-mno-mt
Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns offthis option.
as -mno-mt ...
-mno-mcu
Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. -mno-mcu turnsoff this option.
as -mno-mcu ...
-mno-insn32
Only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any16-bit instructions. This is equivalent to putting ".set insn32" at the start of the assembly file. -mno-insn32 turns off thisoption. This is equivalent to putting ".set noinsn32" at the start of the assembly file. By default -mno-insn32 is selected,allowing all instructions to be used.
as -mno-insn32 ...
--no-construct-floats
The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves ofthe value into the two single width floating point registers that make up the double width register. By default
as --no-construct-floats ...
--construct-floats
allowing construction of these floating point constants.
as --construct-floats ...
--no-relax-branch
The --relax-branch option enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, causing anyout-of-range branches to produce an error.
as --no-relax-branch ...
-mno-ignore-branch-isa
Ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA modeswitch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's targetlabel. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isadisables these checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition betweenISA modes to produce an error.
as -mno-ignore-branch-isa ...
-mnan
Select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default.
as -mnan ...
--emulation
This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFFsupport was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility.The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output isalways ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferredoptions instead.
as --emulation ...
-nocpp
as ignores this option. It is accepted for compatibility with the native tools.
as -nocpp ...
--no-break
Control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trapexception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and thedefault) take a break exception.
as --no-break ...
-O1"
Optimize for performance.
as -O1" ...
-Os"
Optimize for space.
as -Os" ...
-EL"
Produce little endian data output.
as -EL" ...
-EB"
Produce little endian data output.
as -EB" ...
-mno-fp-as-gp-relax"
Suppress fp-as-gp relaxation for this file.
as -mno-fp-as-gp-relax" ...
-mb2bb-relax"
Back-to-back branch optimization.
as -mb2bb-relax" ...
-mno-all-relax"
Suppress all relaxation for this file.
as -mno-all-relax" ...
-march=<arch
Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s.
as -march=<arch ...
-mbaseline
Assemble for baseline <baseline> which could be v2, v3, v3m.
as -mbaseline ...
-mfpu-freg
Specify a FPU configuration."0 8 SP / 4 DP registers""1 16 SP / 8 DP registers""2 32 SP / 16 DP registers""3 32 SP / 32 DP registers"
as -mfpu-freg ...
-m[no-]mac"
Enable/Disable Multiply instructions support.
as -m[no-]mac" ...
-m[no-]div"
Enable/Disable Divide instructions support.
as -m[no-]div" ...
-m[no-]16bit-ext"
Enable/Disable 16-bit extension
as -m[no-]16bit-ext" ...
-m[no-]dx-regs"
Enable/Disable d0/d1 registers
as -m[no-]dx-regs" ...
-m[no-]perf-ext"
Enable/Disable Performance extension
as -m[no-]perf-ext" ...
-m[no-]perf2-ext"
Enable/Disable Performance extension 2
as -m[no-]perf2-ext" ...
-m[no-]string-ext"
Enable/Disable String extension
as -m[no-]string-ext" ...
-m[no-]reduced-regs"
Enable/Disable Reduced Register configuration (GPR16) option
as -m[no-]reduced-regs" ...
-m[no-]audio-isa-ext"
Enable/Disable AUDIO ISA extension
as -m[no-]audio-isa-ext" ...
-m[no-]fpu-sp-ext"
Enable/Disable FPU SP extension
as -m[no-]fpu-sp-ext" ...
-m[no-]fpu-dp-ext"
Enable/Disable FPU DP extension
as -m[no-]fpu-dp-ext" ...
-m[no-]fpu-fma"
Enable/Disable FPU fused-multiply-add instructions
as -m[no-]fpu-fma" ...
-mall-ext"
Turn on all extensions and instructions supportThe following options are available when as is configured for a PowerPC processor.
as -mall-ext" ...
-a32
Generate ELF32 or XCOFF32.
as -a32 ...
-a64
Generate ELF64 or XCOFF64.
as -a64 ...
-mpwrx
Generate code for POWER/2 (RIOS2).
as -mpwrx ...
-mpwr
Generate code for POWER (RIOS1)
as -mpwr ...
-m601
Generate code for PowerPC 601.
as -m601 ...
-mppc
Generate code for PowerPC 603/604.
as -mppc ...
-m403
Generate code for PowerPC 403/405.
as -m403 ...
-m440
Generate code for PowerPC 440. BookE and some 405 instructions.
as -m440 ...
-m464
Generate code for PowerPC 464.
as -m464 ...
-m476
Generate code for PowerPC 476.
as -m476 ...
-m7400
Generate code for PowerPC 7400/7410/7450/7455.
as -m7400 ...
-m750cl
Generate code for PowerPC 750CL.
as -m750cl ...
-m821
Generate code for PowerPC 821/850/860.
as -m821 ...
-mppc64
Generate code for PowerPC 620/625/630.
as -mppc64 ...
-me500
Generate code for Motorola e500 core complex.
as -me500 ...
-me500mc
Generate code for Freescale e500mc core complex.
as -me500mc ...
-me500mc64
Generate code for Freescale e500mc64 core complex.
as -me500mc64 ...
-me5500
Generate code for Freescale e5500 core complex.
as -me5500 ...
-me6500
Generate code for Freescale e6500 core complex.
as -me6500 ...
-mspe
Generate code for Motorola SPE instructions.
as -mspe ...
-mspe2
Generate code for Freescale SPE2 instructions.
as -mspe2 ...
-mtitan
Generate code for AppliedMicro Titan core complex.
as -mtitan ...
-mppc64bridge
Generate code for PowerPC 64, including bridge insns.
as -mppc64bridge ...
-mbooke
Generate code for 32-bit BookE.
as -mbooke ...
-ma2
Generate code for A2 architecture.
as -ma2 ...
-me300
Generate code for PowerPC e300 family.
as -me300 ...
-maltivec
Generate code for processors with AltiVec instructions.
as -maltivec ...
-mvle
Generate code for Freescale PowerPC VLE instructions.
as -mvle ...
-mvsx
Generate code for processors with Vector-Scalar (VSX) instructions.
as -mvsx ...
-mhtm
Generate code for processors with Hardware Transactional Memory instructions.
as -mhtm ...
-mpower4
Generate code for Power4 architecture.
as -mpower4 ...
-mpower5
Generate code for Power5 architecture.
as -mpower5 ...
-mpower6
Generate code for Power6 architecture.
as -mpower6 ...
-mpower7
Generate code for Power7 architecture.
as -mpower7 ...
-mpower8
Generate code for Power8 architecture.
as -mpower8 ...
-mpower9
Generate code for Power9 architecture.
as -mpower9 ...
-mcell
Generate code for Cell Broadband Engine architecture.
as -mcell ...
-mcom
Generate code Power/PowerPC common instructions.
as -mcom ...
-many
Generate code for any architecture (PWR/PWRX/PPC).
as -many ...
-mregnames
Allow symbolic names for registers.
as -mregnames ...
-mno-regnames
Do not allow symbolic names for registers.
as -mno-regnames ...
-mrelocatable
Support for GCC's -mrelocatable option.
as -mrelocatable ...
-mrelocatable-lib
Support for GCC's -mrelocatable-lib option.
as -mrelocatable-lib ...
-memb
Set PPC_EMB bit in ELF flags.
as -memb ...
-mlittle
Generate code for a little endian machine.
as -mlittle ...
-mbig
Generate code for a big endian machine.
as -mbig ...
-msolaris
Generate code for Solaris.
as -msolaris ...
-mno-solaris
Do not generate code for Solaris.
as -mno-solaris ...
-nops
If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops.The following options are available when as is configured for a RISC-V processor.
as -nops ...
-fPIC
Generate position-independent code
as -fPIC ...
-fno-pic
Don't generate position-independent code (default)
as -fno-pic ...
-m64
Select the word size, either 31/32 bits or 64 bits.
as -m64 ...
-mzarch
Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch).
as -mzarch ...
-mwarn-areg-zero
Warn whenever the operand for a base or index register has been specified but evaluates to zero.The following options are available when as is configured for a TMS320C6000 processor.
as -mwarn-areg-zero ...
-mno-dsbt
The -mdsbt option causes the assembler to generate the "Tag_ABI_DSBT" attribute with a value of 1, indicating that the code isusing DSBT addressing. The -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does notuse DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together.
as -mno-dsbt ...
-mpid
The -mpid= option causes the assembler to generate the "Tag_ABI_PID" attribute with a value indicating the form of dataaddressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position-independent addressing withGOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option arelinked together.
as -mpid ...
-mno-pic
The -mpic option causes the assembler to generate the "Tag_ABI_PIC" attribute with a value of 1, indicating that the code isusing position-independent code addressing, The "-mno-pic" option, the default, causes the tag to have a value of 0, indicatingposition-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent andposition-independent) are linked together.
as -mno-pic ...
-mlittle-endian
Generate code for the specified endianness. The default is little-endian.The following options are available when as is configured for a TILE-Gx processor.
as -mlittle-endian ...
-m32
Select the word size, either 32 bits or 64 bits.
as -m32 ...
--text-section-literals
Control the treatment of literal pools. The default is --no-text-section-literals, which places literals in separate sections inthe output file. This allows the literal pool to be placed in a data RAM/ROM. With --text-section-literals, the literals areinterspersed in the text section in order to keep them as close as possible to their references. This may be necessary for largeassembly files, where the literals would otherwise be out of range of the "L32R" instructions in the text section. Literals aregrouped into pools following ".literal_position" directives or preceding "ENTRY" instructions. These options only affectliterals referenced via PC-relative "L32R" instructions; literals for absolute mode "L32R" instructions are handled separately.
as --text-section-literals ...
--auto-litpools
Control the treatment of literal pools. The default is --no-auto-litpools, which in the absence of --text-section-literalsplaces literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With
as --auto-litpools ...
--absolute-literals
Indicate to the assembler whether "L32R" instructions use absolute or PC-relative addressing. If the processor includes theabsolute addressing option, the default is to use absolute "L32R" relocations. Otherwise, only the PC-relative "L32R"relocations can be used.
as --absolute-literals ...
--target-align
Enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled bydefault. Note that the assembler will always align instructions like "LOOP" that have fixed alignment requirements.
as --target-align ...
--longcalls
Enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option shouldbe used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker cangenerally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls.
as --longcalls ...
--transform
Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The defaultis --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in theassembly source. Using --no-transform causes out of range instruction operands to be errors.
as --transform ...
--rename-section
Rename the oldname section to newname. This option can be used multiple times to rename multiple sections.
as --rename-section ...
--trampolines
Enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. This option shouldbe used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size orperformance. The default is --trampolines.The following options are available when as is configured for a Z80 family processor.
as --trampolines ...
-z80
Assemble for Z80 processor.
as -z80 ...
-r800
Assemble for R800 processor.
as -r800 ...
-Wnud
Assemble undocumented Z80 instructions that also work on R800 without warning.
as -Wnud ...
-Wnup
Assemble all undocumented Z80 instructions without warning.
as -Wnup ...
-Wud
Issue a warning for undocumented Z80 instructions that also work on R800.
as -Wud ...
-Wup
Issue a warning for undocumented Z80 instructions that do not work on R800.
as -Wup ...
-Fud
Treat all undocumented instructions as errors.
as -Fud ...
-Fup
Treat undocumented Z80 instructions that do not work on R800 as errors.
as -Fup ...